LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deployment

arXiv:2511.12340v2 Announce Type: replace Abstract: Efficient machine learning deployment requires models that account for hardware constraints. Because binary logic gates are the fundamental primitives of digital hardware, models built directly from logic operations offer a promising path toward highly energy-efficient computation. Recent work has shown that networks of binary logic gates can be trained with gradient-based optimization and that their wiring can be learned. However, existing approaches remain limited in scalability and training efficiency. We address these challenges by treating the network connectome as a differentiable object and introducing a Top-K connectivity mechanism that enforces structured sparsity during training. Our resulting architecture, LILogicNet, substantially improves the efficiency of logic-gate networks. A model with only 8,000 gates trains on MNIST in under five minutes while achieving 98.45% test accuracy, matching the performance of state-of-the-art logic-gate models that require two orders of magnitude more gates. At larger scales, a 256,000-gate model achieves 60.98% test accuracy on CIFAR-10, surpassing prior approaches with comparable gate budgets. Because the final model is fully binarized and composed entirely of logic operations, inference incurs minimal compute overhead and maps naturally to a wide range of digital hardware platforms, enabling efficient deployment across diverse computing systems.